The design of a computer system may be broken down into three parts-system design, logic design, and circuit design. System design involves breaking the overall system into subsystems and specifying the characteristics of each subsystem. For example, system design of a computer system could involve specifying the number and type of memory units, arithmetic units, and input-output devices as well as the interconnection and control of these subsystems. Logic design involves determining how to interconnect basic logic building blocks to perform a specific function. An example of logic design is determining the interconnection of logic gates and flip-flops to perform binary addition. Circuit design involves specifying the interconnection of specific components such as resistors, diodes, and transistors to form a gate, flip-flop, or other logic building block.
A logic building block evaluates its input(s) and outputs a result based on the type of function that the logic building block performs. For example, an AND logic gate, a type of logic building block, outputs logic low whenever one of its inputs is logic low and outputs logic high when all of its inputs are logic high. Alternatively, an OR logic gate outputs logic high whenever one of its inputs is logic high and outputs logic low when all of its inputs are logic low. The number of inputs that a logic building block has is referred to as its xe2x80x9cfan-in.xe2x80x9d In other words, fan-in refers to the number of devices that are driving another device.
An important aspect of circuit design is how logic building blocks, such as logic gates, are actually implemented in a computer system. A typical approach used to implement logic building blocks is through the use of complementary metal-oxide-semiconductor (xe2x80x9cCMOSxe2x80x9d) logic families.
CMOS logic families use metal-oxide-semiconductor field-effect (xe2x80x9cMOSFETxe2x80x9d) transistors. The use of MOSFET transistors is beneficial because almost no current is needed to operate the transistors. However, MOSFETs operate slower than devices used in other logic families. MOSFETs may be divided into two types of transistors: positive-channel metal-oxide semiconductor (xe2x80x9cPMOSxe2x80x9d) transistors and negative-channel metal-oxide semiconductor (xe2x80x9cNMOSxe2x80x9d) transistors. A transistor is xe2x80x98onxe2x80x99 when there is an electrical pathway across the transistor such that a voltage at one terminal of the transistor can be seen at another terminal of the transistor. NMOS transistors can be switched xe2x80x98onxe2x80x99 or xe2x80x98offxe2x80x99 by the movement of electrons, whereas PMOS transistors can be switched xe2x80x98onxe2x80x99 or xe2x80x98offxe2x80x99 by the movement of electron vacancies. A MOSFET has a voltage threshold (xe2x80x9cVTxe2x80x9d) value, which is the voltage level at which the MOSFET switches xe2x80x98onxe2x80x99 or xe2x80x98off.xe2x80x99 Generally, a NMOS transistor switches xe2x80x98onxe2x80x99 when there is a high voltage applied to the input of the NMOS transistor and a PMOS transistor switches xe2x80x98onxe2x80x99 when there is a low voltage, e.g., ground, applied to the input of the PMOS transistor.
Two types of logic gates are static logic gates and dynamic logic gates. Typically, static logic gates have a PMOS and a NMOS transistor for every input. Therefore, with higher fan-in, static logic gates require increased space since the number of transistors needed increases faster than the number of inputs.
Generally, both types of logic gates operate using voltage mode logic. Voltage mode logic is a type of implementation in which circuit behavior is based on a voltage source.
FIG. 1 shows a prior art embodiment of a static logic gate. Specifically, FIG. 1 shows an OR gate (11).
Inputs IN1, IN2, . . . , INn serve as inputs to PMOS transistors P1, P2, . . . , Pn (13, 15, 17) (also referred to as xe2x80x9cPMOS input transistorsxe2x80x9d), respectively, where n represents the number of inputs to the OR gate (11). Inputs IN1, IN2, . . . , INn also serves as inputs to NMOS transistors N1, N2, . . . , Nn (19, 21, 23) (referred to as xe2x80x9cNMOS input transistorsxe2x80x9d), respectively, where n represents the number of inputs to the OR gate (11).
The PMOS input transistors (13, 15, 17) are arranged in series with P1 (13) having a terminal connected to high (25), i.e., a voltage source, and Pn (17) having a terminal connected to a static node, STAT_NODE. The NMOS input transistors (19, 21, 23) are arranged in parallel with each NMOS input transistor (19, 21, 23) having a terminal connected to STAT_NODE and another terminal connected to low (27), i.e., ground. Further, wire resistances (5) are shown on STAT_NODE since a finite amount of voltage is dissipated on STAT_NODE due to these wire resistances (5).
STAT_NODE serves as an input to an inverter (29), which, in turn, outputs a logic voltage to an output, OUT, of the OR gate (11).
When all the inputs to the OR gate (11) are low, the PMOS input transistors (13, 15, 17) are all switched xe2x80x98on,xe2x80x99 and STAT_NODE gets connected to high (25) through the PMOS input transistors (13, 15, 17). In this case, the inverter (29) inputs high from STAT_NODE and outputs low to OUT.
When one or more of the inputs to the OR gate (11) are high, the corresponding NMOS input transistors switch xe2x80x98onxe2x80x99 and the corresponding PMOS input transistors switch xe2x80x98off.xe2x80x99 In this case, STAT_NODE gets connected to low (27) through the xe2x80x98onxe2x80x99 NMOS input transistors. Moreover, since one or more of the PMOS input transistors are xe2x80x98off,xe2x80x99 there is no connection between STAT_NODE and high (25). Thereafter, the inverter (29) inputs low from STAT_NODE and outputs high to OUT.
Dynamic logic gates are often used in place of static logic gates when speed, space, and flexibility are important. Typically, dynamic logic gates use a precharged node that replaces the transistors in series used in static logic gates. The dynamic implementation thus uses lesser space, and speed is increased since wait time for transistor switching is decreased.
Referring to FIG. 2, a prior art embodiment of a dynamic logic gate is shown. Specifically, FIG. 2 shows an OR gate (10).
The OR gate (10) includes a logic evaluation stage (12), which has inputs IN1, IN2, . . . , INn, which serve as inputs to transistors N1, N2, . . . , Nn (14, 16, 18) (referred to as xe2x80x9cinput transistorsxe2x80x9d), where n represents the number of inputs to the OR gate (10). Each input transistor (14, 16, 18) has a terminal connected to dynamic node DYN_NODE, and another terminal connected to a terminal of an NMOS transistor (20) that resides outside the logic evaluation stage (12) (referred to as xe2x80x9coutside NMOS transistor (20)xe2x80x9d).
The outside NMOS transistor (20), in addition to having a terminal connected to select terminals of the input transistors (14, 16, 18) inside the logic evaluation stage (12), has another terminal connected to low (22). Moreover, a clock signal, CLK, serves as an input to the outside NMOS transistor (20).
DYN_NODE is connected to a terminal of a first PMOS transistor (24), and DYN_NODE is also connected to a terminal of a second PMOS transistor (30). Additionally, DYN_NODE serves as an input to an inverter (28), which, in turn, outputs to both an input of the second PMOS transistor (30) and to the output, OUT, of the OR gate (10). Further, wire resistances (19) are shown on DYN_NODE since a finite amount of voltage is dissipated on DYN_NODE due to these wire resistances (19).
The first PMOS transistor (24), in addition to having a terminal connected to DYN_NODE, has a terminal connected to high (26). The second PMOS transistor (30), in addition to having a terminal connected to DYN_NODE, also has a terminal connected to high (26). Moreover, CLK serves as an input to the first PMOS transistor (24).
When CLK goes low, the first PMOS transistor (24) switches xe2x80x98on,xe2x80x99 and DYN_NODE gets connected to high (26) through the first PMOS transistor (24). The inverter (28), in turn, inputs high and outputs low to both the input of the second PMOS transistor (30) and OUT. Since the input to the second PMOS transistor (30) goes low, the second PMOS transistor (30) switches xe2x80x98on,xe2x80x99 causing DYN_NODE to also get connected to high (26) through the second PMOS transistor (30). It follows that when CLK goes high, although the first PMOS transistor (24) switches xe2x80x98off,xe2x80x99 DYN_NODE is still high since it remains connected to high (26) through the second PMOS transistor (30). Thus, DYN_NODE is said to be xe2x80x9cprechargedxe2x80x9d high.
When one (or more) of the inputs to the OR gate (10) goes high, the input transistor corresponding to that input switches xe2x80x98on,xe2x80x99 and DYN_NODE gets connected to a terminal of the outside NMOS transistor (20). When CLK goes high, the outside NMOS transistor (20) switches xe2x80x98on,xe2x80x99 and DYN_NODE gets connected to low (22) through the outside NMOS transistor (20). At this point, although DYN_NODE is momentarily connected to both high (26) through the second PMOS transistor (30) and low (22) through the outside NMOS transistor (20), the outside NMOS transistor (20) out drives the second PMOS transistor (30) since the outside NMOS transistor (20) is sized such that it is stronger than the second PMOS transistor (30), and DYN_NODE goes low.
As DYN_NODE goes low, the inverter (28) outputs high at OUT. The inverter (28) also outputs high to the input of the second PMOS transistor (30), causing the second PMOS transistor (30) to switch xe2x80x98off.xe2x80x99
However, at the next falling edge of CLK, the outside NMOS transistor (22) switches xe2x80x98off,xe2x80x99 the first PMOS transistor (24) switches xe2x80x98on,xe2x80x99 and DYN_NODE goes back high since it gets connected to high (26) through the first PMOS transistor (24), and ensuingly, through the second PMOS transistor (30) as described above.
In summary, the OR gate (10) has a dynamic node, DYN_NODE, that is precharged high. When DYN_NODE is high, the OR gate (10) outputs low during both high and low phases of a clock signal. However, whenever one or more inputs to the OR gate (10) go high, DYN_NODE is discharged and the OR gate (10) outputs high until the clock signal goes low.
When logic gates such as the one described above with reference to FIG. 2 have a large number of inputs or high fan-in, i.e., n is large, special considerations come into play. One such consideration is that the amount of current that passes through a transistor in an xe2x80x98offxe2x80x99 state (referred to as xe2x80x9cleakage currentxe2x80x9d) increases as a transistor becomes faster.
For example, in the case of the OR gate (10) described above in reference to FIG. 2, if the input transistors (14, 16, 18) have higher leakage currents, then the output to the OR gate (10) is susceptible to erroneous switching since DYN_NODE becomes prone to voltage dissipation through the outside NMOS transistor (20). In order to combat this phenomenon, the size of the second PMOS transistor (30) (referred to as xe2x80x9ckeeper transistorxe2x80x9d) is increased relative to the size of the outside NMOS transistor (20). With a high number of inputs, the size of the keeper transistor has to be increased even more to combat the total leakage current from all the input transistors. However, increasing the size of the keeper transistor results in a loss of speed, wherein the loss of speed is counteracted by skewing the inverter (28), i.e., designing the inverter (28) to favor a rising transition at its output. Skewing the inverter (28), in turn, leads to less noise immunity at OUT.
In one aspect, a current steering stage for a logic circuit having a logic evaluation stage connected to an evaluation node comprises a current source that sources current to the evaluation node, and a sink device connected to the evaluation node that selectively sinks current from the current source depending upon the logic evaluation stage.
In another aspect, a current steering logic circuit comprises a logic evaluation stage connected to an evaluation node and having a plurality of inputs, a current steering stage connected to the evaluation node, and a current sensor and translator stage connected to the evaluation node.
In another aspect, a method for steering current in a current mode logic circuit having a logic evaluation stage connected to an evaluation node comprises inputting a plurality of inputs, sourcing current to the evaluation node, and selectively steering current between the logic evaluation stage and a sink device depending upon the plurality of inputs.
In another aspect, a method for performing operations in a current mode logic circuit with high fan-in and having a logic evaluation stage comprises inputting a plurality of inputs, sourcing current to an evaluation node, wherein the evaluation node is connected to the logic evaluation stage, selectively steering sourced current from the current source to a sink device depending upon the plurality of inputs, sensing an amount of current flow through a sink device, and selectively translating the sensed amount of current flow through the sink device to an output voltage.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.